library ieee;
use ieee.std_logic_1164.all;

entity adder_tb is
end adder_tb;

architecture behav_tb of adder_tb is
    component adder
        port(
        a, b: in std_logic_vector(31 downto 0);
        s: out std_logic_vector(31 downto 0)
        );
    end component;

    signal a_s, b_s, s_s: std_logic_vector(31 downto 0);

begin
    A0: adder port map(a_s, b_s, s_s);
    process
    begin
        while true loop
            a_s <= x"00000005";
            b_s <= x"00000005";
            wait for 1 ns;
        end loop;
    end process;
end behav_tb;
